Personal Journey & Technical Philosophy

Bridging the gap between silicon physics, robotics, and practical education.

I am Aryan Jaiswal — an Electronics and Communication Engineering student at SRMIST Delhi-NCR and the founder of Alistron. My work focuses on low-voltage memory circuits, embedded instrumentation, and empowering the next generation of engineers through hands-on robotics.

Aryan Jaiswal portrait
Aryan Jaiswal · Delhi-NCR, India

1. The Engineer: Physics, Rigor & Hardware

My discipline in Electronics and Communication Engineering focuses on hardware constraints from the silicon level upward. I examine how gate voltages scale below 1V, how transistor sizing dictates noise margins in SRAM cells in Cadence Virtuoso, and how embedded microcontrollers process real-time tactile inputs without software latency.

Cadence VirtuosoSRAM Memory DesignEmbedded C++

2. The Founder: Alistron & STEM Accessibility

Through Alistron, I work to demystify engineering for young makers and students. Many educational programs teach coding without physical intuition, or introduce robotics through toy kits that conceal how transistors and sensors truly work. Alistron replaces memorization with hands-on making, breadboard wiring, firmware logic, and physical troubleshooting.

School RoboticsSTEM Workshopsalistron.in
Verified Chronology

Academic & Milestone Timeline

Verified educational progression, intellectual property grants, and executive appointments.

2026Official Patent

Registered Design Grant — Brain-Controlled Bionic Hand

The Patent Office, Government of India

Design No. 504827-001 officially granted and registered under the Designs Act 2000. Co-inventor with SRMIST on an AI-driven, brain-controlled prosthetic hand with closed-loop adaptive grasp regulation and tactile feedback.

2026Founder Venture

Scaling Alistron Robotics & STEM Programs

Alistron

Formalized school and college outreach curricula spanning 6 core technology tracks, 4 workshop formats, and practical project builds.

2025 – PresentVLSI Research

Low-Voltage SRAM Memory Cell Analysis in Cadence Virtuoso

SRMIST ECE Research Lab

Began comparative simulation study of 6T and 8T SRAM topologies under sub-1V VDD scaling to investigate static noise margins and leakage trade-offs.

2024 – PresentLeadership

President of Electronica@SRM & Vice President of NSS Cell

SRMIST Delhi-NCR

Elected to lead departmental technical symposia, undergraduate circuit labs, and campus-wide community welfare programs.

2023B.Tech Inception

Commenced B.Tech in Electronics & Communication Engineering

SRM Institute of Science and Technology

Began undergraduate engineering studies (current CGPA: 7.69), building fundamental skills in circuit theory, semiconductor physics, microcontrollers, and digital electronics.

2023 & 2021Schooling

Completed Senior Secondary (XII: 71%) & Secondary (X: 91.3%)

Basant Valley Public School, Delhi-NCR

Built disciplined foundations in physics, chemistry, and mathematics with analytical honors.

Academic Credentials

B.Tech in Electronics and Communication Engineering
CGPA: 7.69
SRM Institute of Science and Technology · Delhi-NCR Campus (Ghaziabad), India
2023 – Present
Senior Secondary (Class XII), PCM
71%
Basant Valley Public School · Delhi-NCR, India
2023
Secondary School (Class X)
91.3%
Basant Valley Public School · Delhi-NCR, India
2021

Executive Leadership

President — Electronica@SRM
Active Role
  • •Leading the departmental technical society for Electronics and Communication Engineering.
  • •Organizing technical symposiums, hands-on circuit prototyping bootcamps, and VLSI seminars for undergraduate engineers.
  • •Mentoring junior students in hardware debugging, PCB layout fundamentals, and embedded C programming.
Vice President — NSS Cell – SRMIST Delhi-NCR
Active Role
  • •Overseeing community engagement, national service activities, and grassroots outreach programs.
  • •Coordinating institutional blood donation drives, educational awareness camps, and social development initiatives.

Review Official Credentials or Initiate Contact

Download the official VLSI resume or explore collaboration channels.