Engineering, from physical systems to intelligent software.
My engineering interests span semiconductor design, embedded systems, robotics, instrumentation, and software. I approach projects by connecting underlying hardware constraints with system architecture, experimentation, and practical implementation.
VLSI Design & Low-Voltage SRAM Research
Transistor-level digital schematic capture, sub-1V supply voltage scaling, and characterization of memory cell stability in Cadence Virtuoso.
Shared Access Port Constraints
Cross-coupled CMOS inverters with direct pass-gate access. As VDD scales below 0.8V, voltage divider action during read cycles elevates the storage node voltage (VQ), compromising Read Static Noise Margin (RSNM) and inducing read upsets.
Decoupled Read Buffer Solution
Augments the storage core with an independent 2-transistor read stack. Read discharge is isolated from internal nodes, preserving Read SNM identical to Hold SNM and enabling reliable operation down to near-threshold supply voltages.
Low-Voltage SRAM Bitcell Waveform Analyzer
Simulate transient read/write noise margins, access delays, and subthreshold leakage across supply voltages down to near-threshold sub-1.0V regimes.
Decoupled 8T bitcell adds a two-transistor read buffer (M7-M8) driven by read wordline RWL and read bitline RBL, enabling sub-0.8V scaling without sacrificing data stability.
Embedded Systems & Telemetry Instrumentation
Interfacing physical transducers, managing low-power sleep modes, parsing serial NMEA protocols, and engineering resilient telemetry links over Sub-GHz LoRa and cellular modems.
I2C/SPI sensor integration: optical dust counters (PM2.5/PM10), ambient temperature, force-sensing resistors, and ultrasonic transducers with hardware interrupt debouncing.
Sub-GHz LoRa RF communications for remote off-grid monitoring; dual-band GSM/LTE modems driven via deterministic AT command sequences and checksum verification.
Hardware-driven interrupt wake-up routines, cyclic sleep scheduling, and quiescent current management enabling extended multi-day battery readiness.
Robotics, Articulation & Adaptive Neural Control
Formulating anthropomorphic 5-finger mechanical kinematics, adaptive grasp pressure regulation, and cutaneous haptic feedback loops for prosthetic accessibility.
Brain-Controlled Robotic Hand with Adaptive Artificial Intelligence and Haptic Feedback
Design registered and granted by the Patent Office, Government of India, under the Designs Act, 2000 (Design No. 504827-001). Co-inventor listed alongside SRM Institute of Science and Technology.
Embedded algorithm evaluating fingertip tactile feedback to detect micro-slip events and automatically modulate servo torque, preventing delicate objects from crushing or dropping.
Micro-vibrotactile actuators delivering pulse-frequency feedback proportional to surface contact force, re-establishing closed-loop sensory awareness for the wearer.
Scientific Computing, Simulation & Full-Stack Tooling
Connecting mathematical models with interactive browser interfaces, automated SPICE netlist generators, and high-performance Python data pipelines.
EDA Tooling: RLC Frequency Simulator
Built a complete computer-aided circuit analysis platform in Python, NumPy, Flask, and React. Computes resonance, Quality factor (Q), and generates automated standard SPICE `.cir` netlists with interactive Bode plots.
Security Systems: Mini Firewall Simulator
Designed and implemented a network packet filtering simulator in Python, evaluating incoming/outgoing TCP and UDP streams against 5-tuple security rules with automated access logs.
The 6-Stage Engineering Process
How abstract principles transform into verified schematics, prototypes, and intellectual property.
Define the Physical Problem
Isolate fundamental physical, circuit, or operational friction before specifying software abstractions or hardware layouts.
Establish Engineering Constraints
Quantify real boundaries: gate leakage power, supply voltage limits, mass budgets (<450g), signal noise, and real-time latency thresholds (<100ms).
Synthesize Architecture
Formulate schematic topologies, decoupling buffer nodes, finite-state machine flows, and mathematical transfer kernels.
Implementation & Netlisting
Draft transistor-level schematics in Cadence Virtuoso, write embedded C++ firmware for microcontrollers, or model vector equations in Python.
Empirical Simulation & Evaluation
Execute DC butterfly sweeps, testbench transient analysis, corner simulations (-40°C to +85°C), and prototype bench evaluations.
Document Constraints & Future Tapeout
Honestly document parasitic limitations, silicon area penalties (~30% in 8T), and requirements for post-layout verification.
Ready to examine specific project implementations?
Browse the project directory, review the patent certificate, or get in touch.