Comparative Study of 6T and 8T SRAM Cells under Low-Voltage Operation
Cadence Virtuoso transistor-level simulation evaluating stability margins and leakage at sub-1V VDD
In-depth semiconductor research comparing standard 6T and decoupled 8T static RAM cell architectures under aggressive supply-voltage scaling, analyzing Static Noise Margin (SNM), read-disturb vulnerabilities, and leakage power.
The Fundamental Engineering Problem
As supply voltages scale below 0.8V to minimize active power in IoT and edge hardware, standard 6T SRAM cells encounter dramatic degradation in Read Static Noise Margin (RSNM) due to voltage-divider action at storage nodes, leading to destructive read upsets.
Critical Engineering Constraints:
As threshold voltage (Vth) scales to maintain speed at lower VDD, sub-threshold leakage current grows exponentially (Isub ∝ exp((Vgs-Vth)/nVT)), dominating standby battery drain.
In conventional 6T SRAM, pull-down NMOS transistors must be stronger than access transistors for read stability, while access transistors must overpower pull-up PMOS for write-ability.
At sub-1V VDD, the opening of the DC butterfly curve (RSNM) shrinks drastically. Process variations and threshold mismatches can flip the stored bit during a simple read operation.
6T Standard Cell vs 8T Decoupled Topology
Built complete transistor-level schematic topologies in Cadence Virtuoso. Simulated DC butterfly curves to extract Hold SNM, Read SNM, and Write Trip Voltage (WTV) across varying VDD supply levels, evaluating how the decoupled read buffer of the 8T topology alleviates read-disturb.
Low-Voltage SRAM Bitcell Waveform Analyzer
Simulate transient read/write noise margins, access delays, and subthreshold leakage across supply voltages down to near-threshold sub-1.0V regimes.
Decoupled 8T bitcell adds a two-transistor read buffer (M7-M8) driven by read wordline RWL and read bitline RBL, enabling sub-0.8V scaling without sacrificing data stability.
My Specific Contribution to this System
Designed full schematic netlists, set up automated parametric sweeps across supply voltages and process corners, and analyzed stability margins versus silicon area trade-offs.
Constructed transistor-level schematics for both 6T and 8T topologies using predictive technology models, meticulously defining W/L aspect ratios for drive strength balance.
Configured DC sweep testbenches in Cadence Spectre. Swept internal nodes to generate inverted voltage transfer curves (VTC) and calculated the maximum inscribed square representing SNM.
Swept supply voltage (VDD) from 1.2V down to 0.6V in 100mV decrements. Recorded Hold SNM, Read SNM, and Write Trip Margin across nominal and slow process corners.
Simulated total static leakage currents during hold state and quantified the ~30% physical area penalty incurred by the two additional read-port NMOS transistors in 8T.
Empirical Findings & Registered Outcomes
- Cadence Virtuoso simulations confirmed that 8T read noise margin remains virtually unaffected by read-access wordline activation, whereas 6T RSNM degraded by over 45% at 0.7V VDD.
- Write margin in 8T maintained high reliability because pull-up PMOS sizing can be weakened to favor writeability without compromising read stability.
- Subthreshold leakage currents mapped across temperature corners (-40°C to 85°C).
- •All findings currently derived from transistor-level Cadence Virtuoso / Spectre simulations using predictive models; no physical silicon chip fabrication has yet taken place.
- •Interconnect parasitic RC effects from metal layers will introduce additional delay when placed in a multi-megabit memory array layout.
- •Full custom layout generation in Cadence Virtuoso Layout XL with DRC and LVS verification.
- •Post-layout parasitic extraction (PEX) to assess dynamic power and delay penalties.
- •Exploring sub-45nm FinFET and GAA (Gate-All-Around) architectures for near-threshold computing.