Comparative Study of 6T and 8T SRAM Cells under Low-Voltage Operation
Transistor-Level Simulation & Static Noise Margin Analysis in Cadence Virtuoso
As Internet of Things (IoT) edge processors and biomedical implants transition into sub-threshold and near-threshold supply regimes, on-chip SRAM cache memories represent the primary bottleneck for active stability and static power leakage. This research compares standard 6T architectures against decoupled 8T topologies to evaluate empirical boundaries for low-voltage memory operation.
This semiconductor research is actively conducted within the SRMIST ECE simulation laboratory using Cadence Virtuoso and the Spectre Circuit Simulator. All data presented reflects transistor-level SPICE simulations under predictive technology models. Physical silicon tape-out and post-fabrication micro-probing are unverified future milestones.
The Low-Voltage Scaling Wall in Embedded SRAM
Why conventional 6-transistor memory cells encounter destructive read upsets as supply voltages drop.
1. Read-Disturb Mechanism in Standard 6T Cells
A conventional 6T cell relies on cross-coupled CMOS inverters accessed via two NMOS pass-gate transistors. During a read cycle, bitlines are pre-charged to VDD, and the wordline is pulsed high. Current flows from the pre-charged bitline through the access transistor and pull-down NMOS to ground.
This current creates an instantaneous resistive voltage divider across the access and pull-down devices. The voltage at storage node Q (storing logic '0') rises by ΔV. If supply voltage VDD is scaled down to 0.7V or below, this ΔV elevation easily exceeds the switching threshold of the opposing inverter, instantaneously destroying the stored data bit.
2. Subthreshold Leakage Domination
To maintain transistor drive currents at lower VDD, device threshold voltages (Vth) must be lowered. However, subthreshold leakage current is exponentially coupled to threshold voltage:
In standby modes, millions of inactive cells in a memory array continuously leak power, depleting battery reserves in wearable and edge devices even when no compute operations are occurring.
Cadence Virtuoso Simulation Environment
Transistor-level schematic testbenches, DC sweep algorithms, and stability margin extractions.
Schematic Capture
Constructed full complementary schematics for 6T and 8T bitcells. Explicitly sized transistor aspect ratios (Beta ratio β = (W/L)_pulldown / (W/L)_access and Gamma ratio γ = (W/L)_pullup / (W/L)_access) to balance read stability and writeability.
DC Butterfly Curves
Simulated Voltage Transfer Characteristics (VTC) of internal cross-coupled inverters. Extracted Static Noise Margin (SNM) as the side length of the maximum square that can be inscribed inside the lobes of the butterfly curve during Hold and Read states.
Spectre Engine Sweeps
Parametrically swept VDD supply voltage from 1.2V down to 0.6V in 100mV decrements. Executed temperature corner sweeps from -40°C to +85°C to capture subthreshold leakage drift and worst-case hold stability.
Real-Time Transient Waveform & Stability Analyzer
Explore how scaling supply voltage from 1.20V down to 0.60V impacts Static Noise Margins and read disturbance.
Low-Voltage SRAM Bitcell Waveform Analyzer
Simulate transient read/write noise margins, access delays, and subthreshold leakage across supply voltages down to near-threshold sub-1.0V regimes.
Decoupled 8T bitcell adds a two-transistor read buffer (M7-M8) driven by read wordline RWL and read bitline RBL, enabling sub-0.8V scaling without sacrificing data stability.
6T Standard Cell vs 8T Decoupled Topology
Examining how the decoupled read buffer eliminates read-disturb at the expense of silicon footprint.
6T Standard CMOS SRAM Cell
Single Shared Port- • 2 Pull-up PMOS (Load Inverter)
- • 2 Pull-down NMOS (Driver Inverter)
- • 2 Access NMOS (Pass Gates)
8T Decoupled CMOS SRAM Cell
Decoupled Read Port- • 6T Core Inverter & Write Pass Gates
- • 1 Read-Access NMOS (RD-WL gate)
- • 1 Read-Driver NMOS (Gate tied to storage node)
Trade-off Matrix (Simulation Findings)
- •No Physical Silicon: Work is strictly simulation-based within Cadence Virtuoso. No chips have been taped out, fabricated, or physically packaged.
- •Layout Parasitics Pending: Metal interconnect RC parasitics and line capacitances have not yet been extracted via post-layout PEX tools.
- •Array Architecture: Column multiplexers, sense amplifiers, and write-assist circuitry are modeled as lumped loads rather than a complete megabit array.
- •Virtuoso Layout XL: Drawing physical DRC- and LVS-clean layouts for both 6T and 8T standard cells in an open-source or academic PDK.
- •FinFET & GAA Exploration: Extending butterfly curve analysis to multi-gate FinFET device models to evaluate gate controllability at 16nm and below.
- •Academic Publication: Preparing simulation logs and methodology for peer-reviewed undergraduate conference submission.
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