RLC Frequency Response Simulator & Automated SPICE Netlist Generator

Full-stack circuit analysis platform with real-time Bode plot visualization and transient solver

A full-stack computer-aided engineering platform for series and parallel RLC network simulation, calculating resonance, quality factor (Q), bandwidth, and generating automated SPICE netlists with real-time Bode plots.

Analysis

AC & Transient

Math Engine

NumPy Vectorized

Latency

< 25ms response

Export

SPICE .cir format

01. Problem Statement & Constraints

The Fundamental Engineering Problem

Undergraduate engineers and hardware hobbyists frequently struggle to visualize how passive component tolerances, parasitic resistance, and damping factors distort high-frequency circuit response before hardware fabrication.

Critical Engineering Constraints:

Numerical Stability in Stiff Differential Equations

Series and parallel resonant networks with extreme Quality factors (Q > 50) generate sharp resonance poles that cause numerical oscillation if step sizes are not adaptive.

Sub-50ms Interactive Latency

Users adjusting resistance, inductance, and capacitance sliders require instantaneous recalculation of Bode magnitude and phase curves without browser thread freezing.

Standard SPICE Netlist Compatibility

Generated netlists must strictly follow Berkeley SPICE syntax to ensure seamless import into industry simulators like LTspice, Ngspice, and Cadence.

02. System Architecture & Methodology

Full-Stack Circuit Simulation Architecture

Engineered mathematical state equations in Python/NumPy exposed through a RESTful Flask API. Built an interactive browser frontend that renders real-time logarithmic magnitude and phase Bode plots, sensitivity curves, and automated downloadable SPICE netlists.

[1]Mathematical Kernel (Python/NumPy): Computes Laplace transfer functions H(s) = Vout(s) / Vin(s), solving for resonant frequency f0 = 1/(2π√LC), bandwidth Δf = f0/Q, and damping factor ζ.

[2]RESTful API Layer (Flask): Exposes stateless evaluation endpoints accepting network topology (series/parallel), component values, and frequency range parameters.

[3]Interactive Visualization (React.js): Custom SVG and Canvas plotting components rendering dual-axis logarithmic Bode diagrams (Magnitude in dB, Phase in degrees).

[4]Netlist Generator: Synthesizes standard SPICE syntax including .AC, .TRAN, and component tolerance cards.

03. Direct Personal Contribution

My Specific Contribution to this System

Developed end-to-end mathematical models, REST API endpoints, interactive frontend visualizations, and netlist syntax generators.

PythonNumPyFlask REST APIReact.jsCanvas / SVG VisualizationSPICE Syntax Engine

04. Implementation Phases

Phase 1: Mathematical State Formulations

Derived impedance expressions Z(jω) for R-L-C combinations, implementing vector calculations in NumPy across 1000 logarithmic frequency steps.

Phase 2: Flask API & Validation Engine

Created modular endpoints with strict parameter validation, preventing division-by-zero on zero-resistance conditions and providing informative warnings on over-damped states.

Phase 3: Interactive Frontend & Dynamic Sliders

Engineered interactive UI controls with logarithmic slider scaling, enabling users to sweep across micro-Henries to Henries and pico-Farads to milli-Farads seamlessly.

Phase 4: SPICE Syntax Synthesis Engine

Implemented an automated netlist builder producing ready-to-run `.cir` files containing standard SPICE directives and transient stimuli.

05. Evidence & Measured Outcomes

Empirical Findings & Registered Outcomes

Verified calculation accuracy against theoretical analytical values and LTspice benchmarks within < 0.1% margin of error.
Benchmarked client-server round-trip latency under 25ms on local networks.
Successfully used by undergraduate peer engineers during circuit theory coursework at SRMIST.

Known Limitations

•Currently assumes ideal components without temperature coefficients or nonlinear saturation in ferrite-core inductors.
•Supports linear passive networks up to 2nd order; higher-order active op-amp filter synthesizers are not yet integrated.

Planned Future Work

•Integration of parasitic equivalent series resistance (ESR) and stray capacitance models.
•Client-side WebAssembly (Wasm) numerical engine to enable offline compute without server calls.
•Export directly to KiCad schematic formats.

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